Selective metalization of electrical connector or socket housing

ABSTRACT

A electrical interconnect adapted to provide an interface between contact pads on an IC device and a PCB, including a multi-layered substrate with a first surface with a plurality of first openings having first cross-sections, a second surface with a plurality of second openings having second cross-sections, and center openings connecting the first and second openings. The contact members include first contact tips extending through the first opening and above the first surface, second contact tips extending through the second openings and above the second surface, and center portions located in the center openings. The center portions include a shape adapted to bias the first and second contact tips toward the IC device and PCB, respectively. A dielectric material different from the material of the substrate is located in at least one of the first opening, the second opening, or the center opening.

This application is a continuation-in-part of U.S. application Ser. No. 13,412,870 (Allowed), entitled Selective Metalization of Electrical Connector or Socket Housing, filed Mar. 6, 2012, which claims the benefit of U.S. Provisional Application No. 61/449,889, filed Mar. 7, 2011, the disclosure of which is hereby incorporated by reference.

The present application is a continuation-in-part of International Application No. PCT/US2011/038845, titled Electrical Connector Insulator Housing, filed Jun. 2, 2011, which claims the benefit of U.S. Provisional Application No. 61/351,114, entitled Electrical Connector Insulator Housing, filed Jun. 3, 2010, which are hereby incorporated by reference in their entireties.

The present application is a continuation-in-part of International Application No. PCT/US2011/062313, titled HIGH PERFORMANCE SURFACE MOUNT ELECTRICAL INTERCONNECT, filed Nov. 29, 2011, which claims the benefit of U.S. Provisional Application No. 61/418,625, filed Dec. 1, 2010, which are hereby incorporated by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates to an electrical interconnect between an integrated circuit (“IC device”) and a printed circuit board (“PCB”). The present disclosure also discloses the use of unique fabrication techniques that merge processes used in the printed circuit and semiconductor packaging industries with the flexibility of additive printing technology to make the present surface mount electrical interconnect.

BACKGROUND OF THE INVENTION

Traditional IC sockets are generally constructed of an injection molded plastic insulator housing that includes stamped and formed copper alloy contact members stitched or inserted into recesses. The assembled IC socket is then generally processed through a reflow oven to attach solder balls to the contact members. During final assembly the contact pads on the printed circuit board (“PCB”) are printed with solder paste or flux and the solder balls on the IC socket are placed in registration with the contact pads. The assembly is then reflowed and the solder balls essentially weld the IC socket to the PCB.

During use, the IC socket receives an IC device, such as a packaged integrated circuit. The contact members electrically couple the terminals on the IC device with the corresponding terminal on the PCB. The terminals on the IC device are typically held against the contact members by applying a load, which is expected to maintain intimate contact and reliable circuit connection throughout the life of the system without a permanent connection. As a result, the IC device can be removed or replaced without the need for reflowing solder connections.

These types of IC sockets and interconnects have been produced in high volume for many years. As IC devices advance to next generation architectures traditional IC sockets have reached mechanical and electrical limitations that require alternate methods. For example, increased terminal count, reduction in the distance between the contacts known as terminal pitch, and signal integrity have been the main drivers that impact the IC socket design. As terminal counts go up, the IC package essentially gets larger due to the additional space needed for the terminals. As the package grows larger, costs go up and the relative flatness of the package and corresponding PCB require compliance between the contact members in the IC socket and the terminal pad to accommodate the topography differences and maintain reliable connection.

As the terminal pitch is decreased the thickness of the insulating walls in the IC socket housing is also decreased. The length of the contact members is frequently increased to optimize the spring properties. Longer contact members also tend to reduce signal integrity and increase contact resistance due to self-heating of power delivering contacts. The thinner insulating walls increase the difficulty of molding and increase latent stresses in the IC socket housing, increasing the risk of warpage during solder reflow. The thinner insulating walls also increase the risk of cross-talk between adjacent contact members.

Traditional IC sockets have reached an electrical performance limit. Next generation IC devices will operate above 5 GHz and beyond and the existing IC sockets do not provide acceptable performance levels without significant revision.

For example, traditional test sockets are manufactured from bulk plastic material that is machined to provide device location features as well as positions for the electrical contacts, which can be stamped and formed, blanked, wire electro-discharge machining processed, conductive elastomer, coil spring probes or several variations. The predominant contact type used in test sockets is the spring probe, which basically consists of two or more metal members that engage each other to create the electrical path biased by a coil spring that provides normal and return force. A major issue with the use of spring probes in test sockets is the electrical performance is degraded by the coil spring which is an inductor, as well as the potential capacitance of the metal members and the relatively high contact resistance due to the various sliding connection point.

BRIEF SUMMARY OF THE INVENTION

The present disclosure is directed to a high performance electrical interconnect between an integrated circuit and a printed circuit board. This approach provides a reliable connection to integrated circuit devices and creates a platform to add electrical and mechanical enhancements to the socket substrate or assembly to address the challenges of next generation interconnect requirements.

The contact members rely on known spring properties and solder joint methods. The layers structure of the housing eliminates the need for contact retention features, greatly reducing the complexity of the component and the tooling required to produce them. In some embodiments, the present interconnect eliminates the need to add solder balls to the assembly, reducing cost and eliminating at least one reflow cycle which can warp or damage the socket. The interconnect can also reduce or redistribute the terminal pitch without the addition of an interposer or daughter substrate.

The multilayered housing creates the potential to add grounding schemes, shielding, power delivery and management within the socket that reduces the number of connections to the PCB and relieves routing constraints while increasing performance.

In one embodiment, the substrate containing the contact members is inverted to expose the terminal which will connect to the printed circuit board during final assembly. This surface of the substrate and exposed contact members can be treated as a field of connection points for further enhancement that provides contact retention, adds circuit features not normally embedded within a socket, adds mechanical features to improve the reliability of the solder joint to the PCA, and provides a platform to add passive and active circuit features to improve electrical performance or internal function and intelligence. The ability to enhance the interconnect to mimic aspects of the IC device package and the PCB allows for reductions in complexity for the IC device package and the PCB, while improving the overall performance of the interconnect and system.

The present disclosure also merges the long-term performance advantages of traditional PCB and semiconductor packaging with the flexibility of additive printing technology. By combining methods used in the PCB fabrication and semiconductor packaging industries, the present disclosure enables fine line high density circuit structures with attractive cost of manufacture.

The present high performance electrical interconnect can be treated as a system of its own by incorporating electrical devices or other passive and active function, such as for example, ground planes, power planes, electrical connections to other circuit members, dielectric layers, conductive traces, transistors, capacitors, resistors, RF antennae, shielding, filters, signal or power altering and enhancing devices, memory devices, embedded IC, and the like. In some embodiments, the electrical devices can be formed using printing technology, adding intelligence to the interconnect assembly.

The present high performance electrical interconnect can be produced digitally, without tooling or costly artwork. The high performance electrical interconnect can be produced as a “Green” product, with dramatic reductions in environmental issues related to the production of conventional flexible circuits.

The use of additive printing processes permits the material set in a given layer to vary. Traditional PCB and flex circuit fabrication methods take sheets of material and stack them up, laminate, and/or drill. The materials in each layer are limited to the materials in a particular sheet. Additive printing technologies permit a wide variety of materials to be applied on a layer with a registration relative to the features of the previous layer. Selective addition of conductive, non-conductive, or semi-conductive materials at precise locations to create a desired effect has the major advantages in tuning impedance or adding electrical function on a given layer. Tuning performance on a layer by layer basis relative to the previous layer greatly enhances electrical performance.

At least one electrical device is optionally printed on a dielectric layer and electrically coupled to at least a portion of the circuit geometry. Optical quality materials can be printed or deposited in at least a portion of the recesses to form optical circuit geometries. Alternatively, optical fibers can be located in the recesses.

The printing process permits the fabrication of functional structures, such as conductive paths and electrical devices, without the use of masks or resists. Features down to about 10 microns can be directly written in a wide variety of functional inks, including metals, ceramics, polymers and adhesives, on virtually any substrate—silicon, glass, polymers, metals and ceramics. The substrates can be planar and non-planar surfaces. The printing process is typically followed by a thermal treatment, such as in a furnace or with a laser, to achieve dense functionalized structures.

The present disclosure is directed to an electrical interconnect adapted to provide an interface between contact pads on an IC device and a PCB. The electrical interconnect includes a multi-layered substrate with a first surface with a plurality of first openings having first cross-sections, a second surface with a plurality of second openings having second cross-sections, and center openings connecting the first and second openings. The center openings include at least one cross-section greater than the first and second cross-sections. A plurality of spring probe contact members are located in the center openings. The contact members include first contact tips extending through the first opening and above the first surface, second contact tips extending through the second openings and above the second surface, and center portions located in the center openings. The center portions of the contact members include a shape adapted to bias the first and second contact tips toward the IC device and PCB, respectively. A dielectric material different from the material of the substrate is located in at least one of the first opening, the second opening, or the center opening.

The center opening typically includes a non-moldable feature. At least two of the layers of the substrate are different materials. In one embodiment, a metalized layer is formed between layers in the substrate that electrically shields the contact members. In another embodiment, the metalizing layer is formed on surfaces of at least one of the first opening, the second opening, or the center opening. A dielectric material preferably shields the metalized material from the contact members.

In one embodiment the multilayered substrate includes at least one additional circuitry plane selected from one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, or a flexible circuit. At least one electrical device is optionally printed on the substrate and electrically coupled to at least a one of the contact members.

The present disclosure is also directed to an electrical interconnect assembly. A housing retains the electrical interconnect. An IC device is located in an openings in the housing and electrically coupled to the first contact tips of the contact members. The PCB is electrically coupled to the second contact tips of the contact members.

The present disclosure is also directed to a method of making an electrical interconnect to provide an interface between contact pads on an IC device and a PCB. The method includes forming a multi-layered substrate including a first surface with a plurality of first openings having first cross-sections, a second surface with a plurality of second openings having second cross-sections, and center openings connecting the first and second openings. The center openings include at least one cross-section greater than the first and second cross-sections. Spring probe contact members are located in the center openings so first contact tips of the contact members extend through the first opening and above the first surface, second contact tips extending through the second openings and above the second surface, and center portions located in the center openings bias the first and second contact tips toward the IC device and PCB, respectively. A dielectric material different from the material of the substrate is formed in at least one of the first opening, the second opening, or the center opening.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a cross sectional view of an electrical interconnect with a multilayered substrate in accordance with an embodiment of the present disclosure.

FIG. 2 illustrates an electrical interconnect with shielding located in the multilayered substrate in accordance with an alternate embodiment of the present disclosure.

FIG. 3 illustrates an electrical interconnect with alternate shielding located in the multilayered substrate in accordance with an alternate embodiment of the present disclosure.

FIG. 4 illustrates an electrical interconnect with alternate shielding located in the multilayered substrate in accordance with an alternate embodiment of the present disclosure.

FIG. 5 illustrates an electrical interconnect with on-board electrical devices in accordance with an embodiment of the present disclosure.

FIG. 6 illustrates an alternate electrical interconnect with on-board electrical devices in accordance with an embodiment of the present disclosure.

FIG. 7 illustrates an electrical interconnect with capacitive coupling in accordance with an embodiment of the present disclosure.

FIG. 8 is a cross-sectional view of a method of making a high performance electrical interconnects in accordance with an embodiment of the present disclosure.

FIG. 9 illustrates via formation on the high performance electrical interconnect of FIG. 8.

FIG. 10 illustrates application to a second circuitry layer to the high performance electrical interconnect of FIG. 8.

FIG. 11 illustrates an alternate method of making an electrical interconnect in accordance with an embodiment of the present disclosure.

FIG. 12 illustrates application of a second circuitry layer to the electrical interconnect of FIG. 11.

FIG. 13 illustrates another method of making an electrical interconnect in accordance with an embodiment of the present disclosure.

FIG. 14 illustrates via formation on the electrical interconnect of FIG. 13.

FIG. 15 illustrates an electrical interconnect with bulk metal deposited in recesses to form the vias in accordance with an embodiment of the present disclosure.

FIG. 16 illustrates an electrical interconnect with recesses filed with conductive particles as the vias in accordance with an embodiment of the present disclosure.

FIG. 17 is a side sectional view of an electrical interconnect in accordance with an embodiment of the present disclosure.

FIG. 18 is a side sectional view of an alternate electrical interconnect with printed compliant material in accordance with an embodiment of the present disclosure.

FIG. 19 illustrates an electrical interconnect with optical features in accordance with an embodiment of the present disclosure.

FIG. 20 illustrates an alternate high performance electrical interconnect with optical features in accordance with an embodiment of the present disclosure.

FIG. 21 illustrates an alternate high performance electrical interconnect with printed vias in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

A high performance electrical interconnect according to the present disclosure may permit fine contact-to-contact spacing (pitch) on the order of less than 1.0 mm pitch, and more preferably a pitch of less than about 0.7 millimeter, and most preferably a pitch of less than about 0.4 millimeter. Such fine pitch high performance electrical interconnects are especially useful for communications, wireless, and memory devices.

The present high performance electrical interconnect can be configured as a low cost, high signal performance interconnect assembly, which has a low profile that is particularly useful for desktop and mobile PC applications. IC devices can be installed and uninstalled without the need to reflow solder. The solder-free electrical connection of the IC devices is environmentally friendly.

FIG. 1 is a sectional view of an electrical interconnect 50 that provides an interface between IC device 52 and PCB 54 in accordance with an embodiment of the present disclosure. Housing 56 is preferably constructed from a plurality of layers 58A, 58B, 58C, 58D, 58E (“58”).

Contact members 60 are located in recesses 62 formed in the housing 56. In the illustrated embodiment, layers 58A and 58E include shoulders 64 that capture the contact members 60 in the recesses 62. After the contact members 60 are positioned in the recess 62, layer 58E is added to the housing 56 to capture the contact members 60. The layer 58E can be added by printing or can be a preformed layer bonded to the interconnect housing 56. As used herein, “bond” or “bonding” refers to, for example, adhesive bonding, solvent bonding, ultrasonic welding, thermal bonding, or any other techniques suitable for attaching adjacent layers to a substrate.

The contact members 60 include spring 66 engaged with tab 74 on upper contact tip 68 and lower contact tip 72. The contact tip 68 is adapted to slide between beams 70 on lower contact tip 72. The spring 66 biases the upper contact tip 68 toward the IC device 52 and the lower contact tip 72 toward the PCB 54. The lower contact tip 72 is preferably adapted to slide in opening 76 within the layer 58A. When located in the recess 62, the spring 66 is preferably partially compressed.

In the preferred embodiment, the interconnect 50 is part of a socket that receives IC device 52. A separate biasing mechanism (not shown) biases the IC device 52 into engagement with the contact tips 68 and/or the lower contact tip 72 into engagement with the PCB 54.

FIG. 2 illustrates an alternate interconnect 100 in which the interconnect housing 102 includes a series of ground planes 104A, 104B (“104”) in accordance with an embodiment of the present disclosure. The ground planes 104 improve electrical performance and provide shielding for the contact member 108. In one embodiment, the core layers 106A-106F (“106”) of the interconnect housing 102 are plated with a dielectric 105 to prevent the contact member 60 from shorting against the ground plans 104. Multiple ground planes can also be embedded between layers 106.

FIG. 3 illustrates an alternate interconnect 150 where the inner walls 152 of the drilled core 154 are metalized 156 and not tied to ground in accordance with an embodiment of the present disclosure. The metalized walls 156 provide an impedance tuning effect to counteract either the inductance of the coil spring 158 and/or the capacitance of the pin 160, with one or more dielectric materials 162 between the metalized wall 156 and the coil spring 158 or pin 160 to control impedance as well as prevent shorting.

FIG. 4 illustrates an alternate interconnect housing 200 with the inner walls 202 of the core 204 are metalized 206 at strategic locations to provide the desired impedance tuning effect for the contact members 208 in accordance with an embodiment of the present disclosure. Metalizing 206 and any dielectric portions 210 can be located at any position vertically or horizontally between the layers 212A-212G, or on the walls 202 of the cores 204. The metalizing 206 can be altered from contact-to-contact 208 and core-to-core 204, within a given field of contact members to influence the impedance on a pin-by-pin basis should there be a need to mix impedance properties.

FIG. 5 illustrates electrical interconnect 320 with electrical devices 322, such as for example, internal decoupling capacitors, located on substrate 324 in accordance with an embodiment of the present disclosure. Printed conductive traces 326 electrically couple the electrical devices 322 to one or more of the contact pads 328. The electrical devices 322 can be added as discrete components or printed materials, reducing the need for discrete components on the PCB 332 and the integrated circuit device 330. Locating the electrical devices 322 in the semiconductor socket 320 permits integrated circuit manufactures to reduce or eliminate the capacitors currently located on the package 330 and printed circuit board 332. This shift can greatly reduce cost and simplify the package 330 and printed circuit board 332, while improving performance.

The electrical devices 322 can be a power plane, ground plane, capacitor, resistor, filters, signal or power altering and enhancing device, memory device, embedded IC, RF antennae, and the like. The electrical devices 322 can be located on either surface of the substrate 324, or embedded therein. The electrical devices 322 can include passive or active functional elements. Passive structure refers to a structure having a desired electrical, magnetic, or other property, including but not limited to a conductor, resistor, capacitor, inductor, insulator, dielectric, suppressor, filter, varistor, ferromagnet, and the like.

Locating such electrical devices 322 on the electrical interconnect 320 improves performance and enables a reduction in the cost of integrated circuit devices and the PCB 332. Integrated circuit manufactures are limited by the pitch that the PCB 332 can accommodate and still keep the printed circuit board to four layers. The integrated circuit makers can manufacture the integrated circuit device 330 with a smaller pitch, but with the pin counts is so high that the printed circuit board 332 likely requires additional layers in order to route all of the signals. The present electrical interconnect 320 also permits integrated circuit manufactures to reduce the pitch of the contacts on the IC device 330, and perform any required signal routing in the electrical interconnect 320, rather than in the printed circuit board 332 or by adding daughter boards to the system.

FIG. 6 illustrates an alternate electrical interconnect 340 with on-board electrical devices 342 in accordance with an embodiment of the present disclosure. The decoupling capacitance 342 can be a discrete embedded or printed electrical device. Contact member 344 provides the electrical connection to the capacitor located on the semiconductor device 346 and solder ball 348 provides the electrical connection to the capacitor located on printed circuit board 350.

FIG. 7 is a cross-sectional view of electrical interconnect 370 with various capacitive coupling features in accordance with another embodiment of the present disclosure. A capacitive coupling feature 372A is embedded in layer 374 of the substrate 375. A capacitive coupling feature 372B is located on second surface 376 of the layer 374. The capacitive coupling features 372A, 372B are positioned to electrically couple with contact pad 378 on integrated circuit device 380. The capacitive coupling 372C is embedded in layer 388.

Capacitive coupling feature 382A is embedded in layer 384 of the substrate 375. Capacitive coupling feature 382B is located on first surface 386 of the layer 384. The capacitive coupling feature 382A is positioned to electrically couple with contact pad 390 on the PCB 392. The various capacitive coupling features in the embodiment of FIG. 7 are optionally formed using inkjet printing technology, aerosol printing technology, or other printing technology.

FIG. 8 is a side cross-sectional view of a method of making an electrical interconnect 400 using additive processes in accordance with an embodiment of the present disclosure. The process starts similar to a traditional PCB with a first circuitry layer 452 laminated to a stiffening layer or core 450, such as glass-reinforced epoxy laminate sheets (e.g., FR4). The first circuitry layer 452 can be preformed or can be formed using a fine line imaging step is conducted to etch the copper foil 452 as done with many PCB processes. One or more dielectric layers 454, 456 are printed or placed to the surface 458 such that the first circuitry layer 452 is at least partially encased and isolated. In some embodiments, it may be desirable to use a preformed dielectric film to leave air dielectric gaps between traces. Recesses 460 in the dielectric layer 456 to expose circuitry 452 can be formed by printing, embossing, imprinting, chemical etching with a printed mask, or a variety of other techniques.

As illustrated in FIG. 9, bond points 462, such as for example stud bumps or soldier balls, are added to the exposed circuitry 452 with a traditional bonding machine used in semiconductor packaging applications. Historically, fine gold wire has been used for bonding, with copper seeing increased use in recent years due to the rise in the cost of gold.

As illustrated in FIG. 10, second circuitry layer 464 is applied to the previous construction such that the bond points 462 are deformed to create the interconnecting vias 466 during the lamination operation. The size and shape of the bond points 462 can be tailored to the ideal condition for deformation without piercing the foil 464.

The second circuitry layer 464 can be pre-etched with the next circuit pattern or can be laminated as a sheet and etched post lamination. In addition, the dielectric material 456 can be left in a tack cure or partial cure state such that a final bond is achieved at final cure. If desired, the bond bumps 462 can be coined planar prior to adding the second circuitry layer 464.

FIGS. 11 and 12 illustrate an alternate interconnect 468 with preformed holes or breaks 470 in the first circuitry layer 472 in accordance with an embodiment of the present disclosure. The holes 470 permit the bond points 462 to extend into the openings 470 or reside near the openings 470 so plating solution 474 can enter the mating region to plate the via structure 476 together. The plating 474 is preferably a corrosion resistant metallic material such as nickel, gold, silver, palladium, or multiple layers thereof. One benefit of the present structure is the material set can be varied layer by layer or altered on a given layer to create some desired performance enhancement not possible with conventional construction.

FIGS. 13 and 14 illustrate an alternate construction in which bond points 480 are added to the circuitry 482 while it is planar, without upper dielectric layer 484 to provide clearance for the bonding tool to impact the circuitry 482 without encountering or damaging the dielectric 484. The bond points 480 can be coined en masse to planarize them either before or after the dielectric layer 484. In one embodiment, the dielectric layer 484 is added with the bond points 480 in place and then imaged to expose the vias 486 for subsequent application of the next pre-etched circuit layer to be placed and plated together (see e.g., FIGS. 9 and 11). The dielectric layer 484 can optionally be filled or doped with a near endless list of enhancement materials to lower dielectric constant, provide thermal management properties, create rigid, flexible, or compliant regions etc.

FIG. 15 illustrates an alternate electrical interconnect 488 with solid bulk metal 490, such as copper or solder spheres, or plated copper, located in recesses 492 in dielectric layer 494 in accordance with an embodiment of the present disclosure. The bulk metal 490 electrically couples with the lower circuitry layer 496 and the upper circuitry layer 498 with slight deformation or material displacement. In one embodiment, the bulk metal 490 is plated, such as by flowing a plating solution through openings 500 in the upper circuitry 498. It may be possible to provide sufficient engagement to interconnect reliably without the need for plating since the bulk metal 490 is encased within dielectric 494 and environmentally sealed. In the event the bulk metal 490 is solder, the circuit layers 496, 498 can be interconnected when the solder 490 is reflowed with the dielectric 494 acting as a natural solder wicking barrier.

FIG. 16 illustrates an alternate electrical interconnect 510 with reservoirs 512 between circuitry layers 514, 516 that can be filled with loose conductive particles 518 in accordance with an embodiment of the present disclosure. The conductive particles 518 can optionally be sintered, coined, tightly compacted, plated, mixed with an adhesive binder, etc. to create via 520. The method of FIG. 18 can also be used to create the circuitry itself or supplement the etched foil structures. Use of reservoirs containing conductive particles is disclosed in commonly assigned PCT/US2010/36313 entitled Resilient Conductive Electrical Interconnect, filed May 27, 2010, which is hereby incorporated by reference.

FIG. 17 illustrates an alternate electrical interconnect 530 with an insulating layer 532 applied to the circuit geometry 534. The nature of the printing process allows for selective application of dielectric layer 532 to leave selected portions 536 of the circuit geometry 534 expose if desired. The resulting high performance electrical interconnect 530 can potentially be considered entirely “green” with limited or no chemistry used to produce beyond the direct write materials.

The dielectric layers of the present disclosure may be constructed of any of a number of dielectric materials that are currently used to make sockets, semiconductor packaging, and printed circuit boards. Examples may include UV stabilized tetrafunctional epoxy resin systems referred to as Flame Retardant 4 (FR-4); bismaleimide-triazine thermoset epoxy resins referred to as BT-Epoxy or BT Resin; and liquid crystal polymers (LCPs), which are polyester polymers that are extremely unreactive, inert and resistant to fire. Other suitable plastics include phenolics, polyesters, and Ryton® available from Phillips Petroleum Company.

In one embodiment, one or more of the dielectric materials are designed to provide electrostatic dissipation or to reduce cross-talk between the traces of the circuit geometry. An efficient way to prevent electrostatic discharge (“ESD”) is to construct one of the layers from materials that are not too conductive but that will slowly conduct static charges away. These materials preferably have resistivity values in the range of 10⁵ to 10¹¹ Ohm-meters.

FIG. 18 illustrates an alternate high performance electrical interconnect 550 in accordance with an embodiment of the present disclosure. Dielectric layer 552 includes openings 554 into which compliant material 556 is printed before formation of circuit geometry 558. The compliant printed material 556 improves reliability during flexure of the electrical interconnect 550.

FIG. 19 illustrates an alternate high performance electrical interconnect 560 in accordance with an embodiment of the present disclosure. Optical fibers 562 are located between layers 564, 566 of dielectric material. In one embodiment, optical fibers 562 is positioned over printed compliant layer 568, and dielectric layer 570 is printed over and around the optical fibers 562. A compliant layer 572 is preferably printed above the optical fiber 562 as well. The compliant layers 568, 572 support the optical fibers 562 during flexure. In another embodiment, the dielectric layer 570 is formed or printed with recesses into which the optical fibers 562 are deposited.

In another embodiment, optical quality materials 574 are printed during printing of the high performance electrical interconnect 560. The optical quality material 574 and/or the optical fibers 562 comprise optical circuit geometries. The printing process allows for deposition of coatings in-situ that enhance the optical transmission or reduce loss. The precision of the printing process reduces misalignment issues when the optical materials 574 are optically coupled with another optical structure.

FIG. 20 illustrates another embodiment of a present high performance electrical interconnect 580 in accordance with an embodiment of the present disclosure. Embedded coaxial RF circuits 582 or printed micro strip RF circuits 584 are located with dielectric/metal layers 586. These RF circuits 582, 584 are preferably created by printing dielectrics and metallization geometry.

As illustrated in FIG. 21 use of additive processes allows the creation of a high performance electrical interconnect 590 with inter-circuit, 3D lattice structures 592 having intricate routing schemes. Vias 594 can be printed with each layer, without drilling.

The nature of the printing process permit controlled application of dielectric layers 596 creates recesses 598 that control the location, cross section, material content, and aspect ratio of the conductive traces 592 and the vias 594. Maintaining the conductive traces 592 and vias 594 with a cross-section of 1:1 or greater provides greater signal integrity than traditional subtractive trace forming technologies. For example, traditional methods take a sheet of a given thickness and etches the material between the traces away to have a resultant trace that is usually wider than it is thick. The etching process also removes more material at the top surface of the trace than at the bottom, leaving a trace with a trapezoidal cross-sectional shape, degrading signal integrity in some applications. Using the recesses 598 to control the aspect ratio of the conductive traces 592 and the vias 594 results in a more rectangular or square cross-section, with the corresponding improvement in signal integrity.

In another embodiment, pre-patterned or pre-etched thin conductive foil circuit traces are transferred to the recesses 598. For example, a pressure sensitive adhesive can be used to retain the copper foil circuit traces in the recesses 598. The trapezoidal cross-sections of the preformed conductive foil traces are then post-plated. The plating material fills the open spaces in the recesses 598 not occupied by the foil circuit geometry, resulting in a substantially rectangular or square cross-sectional shape corresponding to the shape of the recesses 598.

In another embodiment, a thin conductive foil is pressed into the recesses 598, and the edges of the recesses 598 acts to cut or shear the conductive foil. The process locates a portion of the conductive foil in the recesses 598, but leaves the negative pattern of the conductive foil not wanted outside and above the recesses 598 for easy removal. Again, the foil in the recesses 598 is preferably post plated to add material to increase the thickness of the conductive traces 592 in the circuit geometry and to fill any voids left between the conductive foil and the recesses 598.

The availability of printable silicon inks provides the ability to print the electrical devices, such as disclosed in the patents previously referenced and incorporated herein by reference. For example, the electrical devices can be formed using printing technology, adding intelligence to the present interconnect assembly. In particular, features that are typically located on the IC device or PCB can be incorporated into the interconnect assembly in accordance with an embodiment of the present disclosure.

Locating such electrical devices on the interconnect assembly improves performance and enables a reduction in the cost of the IC device, the package for the IC device, and the PCB. Integrated circuit manufactures are limited by the pitch that the PCB can accommodate and still keep the printed circuit board to four layers. The integrated circuit makers can manufacture the IC device package with a smaller pitch, but with the pin counts is so high that the PCB likely requires additional layers in order to route all of the signals.

The present interconnect assembly permits integrated circuit manufactures to reduce the pitch of the contacts on the IC device package, and perform any required signal routing in the interconnect assembly, rather than in the PCB or by adding daughter boards to the system.

Integrated circuit manufactures also are limited by current socket designs when designing the configuration of contacts on the IC device package. Performing the routing in the present interconnect assembly permits quick and inexpensive changes. Similarly, locating the electrical devices in the interconnect assembly permits integrated circuit manufactures to reduce or eliminate the capacitors currently located on the IC device package and PCB. This shift can greatly reduce cost and simplify the IC device package and PCB, while improving performance.

One of the reasons the contact members on prior art socket are so long (typically about 3 millimeters) is to provide clearance for the capacitors on the IC device package and the PCB when the integrated circuit is put into the socket. Locating transistors and memory in the present interconnect assembly will permit the contact members to be shorter, which will improve the performance of the contacts.

The various embodiments of the present interconnect can include printed electrical devices. The electrical devices can include passive or active functional elements. Passive structure refers to a structure having a desired electrical, magnetic, or other property, including but not limited to a conductor, resistor, capacitor, inductor, insulator, dielectric, suppressor, filter, varistor, ferromagnet, and the like. In the illustrated embodiment, electrical devices include printed LED indicator and display electronics. Geometries can also be printed to provide capacitive coupling. Compliant material can be added between circuit geometry, such as discussed above, so the present electrical interconnect can be plugged into a receptacle or socket, supplementing or replacing the need for compliance within the connector.

The electrical devices are preferably printed during construction of the interconnect assembly. The electrical devices can be ground planes, power planes, electrical connections to other circuit members, dielectric layers, conductive traces, transistors, capacitors, resistors, RF antennae, shielding, filters, signal or power altering and enhancing devices, memory devices, embedded IC, and the like. For example, the electrical devices can be formed using printing technology, adding intelligence to the high performance electrical interconnect. Features that are typically located on other circuit members can be incorporated into the interconnect in accordance with an embodiment of the present disclosure.

The availability of printable silicon inks provides the ability to print electrical devices, such as disclosed in U.S. Pat. No. 7,485,345 (Renn et al.); U.S. Pat. No. 7,382,363 (Albert et al.); U.S. Pat. No. 7,148,128 (Jacobson); U.S. Pat. No. 6,967,640 (Albert et al.); U.S. Pat. No. 6,825,829 (Albert et al.); U.S. Pat. No. 6,750,473 (Amundson et al.); U.S. Pat. No. 6,652,075 (Jacobson); U.S. Pat. No. 6,639,578 (Comiskey et al.); U.S. Pat. No. 6,545,291 (Amundson et al.); U.S. Pat. No. 6,521,489 (Duthaler et al.); U.S. Pat. No. 6,459,418 (Comiskey et al.); U.S. Pat. No. 6,422,687 (Jacobson); U.S. Pat. No. 6,413,790 (Duthaler et al.); U.S. Pat. No. 6,312,971 (Amundson et al.); U.S. Pat. No. 6,252,564 (Albert et al.); U.S. Pat. No. 6,177,921 (Comiskey et al.); U.S. Pat. No. 6,120,588 (Jacobson); U.S. Pat. No. 6,118,426 (Albert et al.); and U.S. Pat. Publication No. 2008/0008822 (Kowalski et al.), which are hereby incorporated by reference. In particular, U.S. Pat. No. 6,506,438 (Duthaler et al.) and U.S. Pat. No. 6,750,473 (Amundson et al.), which are incorporated by reference, teach using ink jet printing to make various electrical devices, such as, resistors, capacitors, diodes, inductors (or elements which may be used in radio applications or magnetic or electric field transmission of power or data), semiconductor logic elements, electro-optical elements, transistor (including, light emitting, light sensing or solar cell elements, field effect transistor, top gate structures), and the like.

The electrical devices can also be created by aerosol printing, such as disclosed in U.S. Pat. No. 7,674,671 (Renn et al.); U.S. Pat. No. 7,658,163 (Renn et al.); U.S. Pat. No. 7,485,345 (Renn et al.); U.S. Pat. No. 7,045,015 (Renn et al.); and U.S. Pat. No. 6,823,124 (Renn et al.), which are hereby incorporated by reference.

Printing processes are preferably used to fabricate various functional structures, such as conductive paths and electrical devices, without the use of masks or resists. Features down to about 10 microns can be directly written in a wide variety of functional inks, including metals, ceramics, polymers and adhesives, on virtually any substrate—silicon, glass, polymers, metals and ceramics. The substrates can be planar and non-planar surfaces. The printing process is typically followed by a thermal treatment, such as in a furnace or with a laser, to achieve dense functionalized structures.

Ink jet printing of electronically active inks can be done on a large class of substrates, without the requirements of standard vacuum processing or etching. The inks may incorporate mechanical, electrical or other properties, such as, conducting, insulating, resistive, magnetic, semi conductive, light modulating, piezoelectric, spin, optoelectronic, thermoelectric or radio frequency.

A plurality of ink drops are dispensed from the print head directly to a substrate or on an intermediate transfer member. The transfer member can be a planar or non-planar structure, such as a drum. The surface of the transfer member can be coated with a non-sticking layer, such as silicone, silicone rubber, or Teflon.

The ink (also referred to as function inks) can include conductive materials, semi-conductive materials (e.g., p-type and n-type semiconducting materials), metallic material, insulating materials, and/or release materials. The ink pattern can be deposited in precise locations on a substrate to create fine lines having a width smaller than 10 microns, with precisely controlled spaces between the lines. For example, the ink drops form an ink pattern corresponding to portions of a transistor, such as a source electrode, a drain electrode, a dielectric layer, a semiconductor layer, or a gate electrode.

The substrate can be an insulating polymer, such as polyethylene terephthalate (PET), polyester, polyethersulphone (PES), polyimide film (e.g. Kapton, available from DuPont located in Wilmington, Del.; Upilex available from Ube Corporation located in Japan), or polycarbonate. Alternatively, the substrate can be made of an insulator such as undoped silicon, glass, or a plastic material. The substrate can also be patterned to serve as an electrode. The substrate can further be a metal foil insulated from the gate electrode by a non-conducting material. The substrate can also be a woven material or paper, planarized or otherwise modified on at least one surface by a polymeric or other coating to accept the other structures.

Electrodes can be printed with metals, such as aluminum or gold, or conductive polymers, such as polythiophene or polyaniline. The electrodes may also include a printed conductor, such as a polymer film comprising metal particles, such as silver or nickel, a printed conductor comprising a polymer film containing graphite or some other conductive carbon material, or a conductive oxide such as tin oxide or indium tin oxide.

Dielectric layers can be printed with a silicon dioxide layer, an insulating polymer, such as polyimide and its derivatives, poly-vinyl phenol, polymethylmethacrylate, polyvinyldenedifluoride, an inorganic oxide, such as metal oxide, an inorganic nitride such as silicon nitride, or an inorganic/organic composite material such as an organic-substituted silicon oxide, or a sol-gel organosilicon glass. Dielectric layers can also include a bicylcobutene derivative (BCB) available from Dow Chemical (Midland, Mich.), spin-on glass, or dispersions of dielectric colloid materials in a binder or solvent.

Semiconductor layers can be printed with polymeric semiconductors, such as, polythiophene, poly(3-alkyl)thiophenes, alkyl-substituted oligothiophene, polythienylenevinylene, poly(para-phenylenevinylene) and doped versions of these polymers. An example of suitable oligomeric semiconductor is alpha-hexathienylene. Horowitz, Organic Field-Effect Transistors, Adv. Mater., 10, No. 5, p. 365 (1998) describes the use of unsubstituted and alkyl-substituted oligothiophenes in transistors. A field effect transistor made with regioregular poly(3-hexylthiophene) as the semiconductor layer is described in Bao et al., Soluble and Processable Regioregular Poly(3-hexylthiophene) for Thin Film Field-Effect Transistor Applications with High Mobility, Appl. Phys. Lett. 69 (26), p. 4108 (December 1996). A field effect transistor made with a-hexathienylene is described in U.S. Pat. No. 5,659,181, which is incorporated herein by reference.

A protective layer can optionally be printed onto the electrical devices. The protective layer can be an aluminum film, a metal oxide coating, a polymeric film, or a combination thereof.

Organic semiconductors can be printed using suitable carbon-based compounds, such as, pentacene, phthalocyanine, benzodithiophene, buckminsterfullerene or other fullerene derivatives, tetracyanonaphthoquinone, and tetrakisimethylanimoethylene. The materials provided above for forming the substrate, the dielectric layer, the electrodes, or the semiconductor layers are exemplary only. Other suitable materials known to those skilled in the art having properties similar to those described above can be used in accordance with the present disclosure.

The ink jet print head preferably includes a plurality of orifices for dispensing one or more fluids onto a desired media, such as for example, a conducting fluid solution, a semiconducting fluid solution, an insulating fluid solution, and a precursor material to facilitate subsequent deposition. The precursor material can be surface active agents, such as octadecyltrichlorosilane (OTS).

Alternatively, a separate print head is used for each fluid solution. The print head nozzles can be held at different potentials to aid in atomization and imparting a charge to the droplets, such as disclosed in U.S. Pat. No. 7,148,128 (Jacobson), which is hereby incorporated by reference. Alternate print heads are disclosed in U.S. Pat. No. 6,626,526 (Ueki et al.), and U.S. Pat. Publication Nos. 2006/0044357 (Andersen et al.) and 2009/0061089 (King et al.), which are hereby incorporated by reference.

The print head preferably uses a pulse-on-demand method, and can employ one of the following methods to dispense the ink drops: piezoelectric, magnetostrictive, electromechanical, electro pneumatic, electrostatic, rapid ink heating, magneto hydrodynamic, or any other technique well known to those skilled in the art. The deposited ink patterns typically undergo a curing step or another processing step before subsequent layers are applied.

While ink jet printing is preferred, the term “printing” is intended to include all forms of printing and coating, including: pre-metered coating such as patch die coating, slot or extrusion coating, slide or cascade coating, and curtain coating; roll coating such as knife over roll coating, forward and reverse roll coating; gravure coating; dip coating; spray coating; meniscus coating; spin coating; brush coating; air knife coating; screen printing processes; electrostatic printing processes; thermal printing processes; and other similar techniques.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range and any other stated or intervening value in that stated range is encompassed within the embodiments of the disclosure. The upper and lower limits of these smaller ranges which may independently be included in the smaller ranges is also encompassed within the embodiments of the disclosure, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either both of those included limits are also included in the embodiments of the present disclosure.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the present disclosure belong. Although any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the embodiments of the present disclosure, the preferred methods and materials are now described. All patents and publications mentioned herein, including those cited in the Background of the application, are hereby incorporated by reference to disclose and described the methods and/or materials in connection with which the publications are cited.

The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present disclosure is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.

Other embodiments of the disclosure are possible. Although the description above contains much specificity, these should not be construed as limiting the scope of the disclosure, but as merely providing illustrations of some of the presently preferred embodiments of this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the present disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments of the disclosure. Thus, it is intended that the scope of the present disclosure herein disclosed should not be limited by the particular disclosed embodiments described above.

Thus the scope of this disclosure should be determined by the appended claims and their legal equivalents. Therefore, it will be appreciated that the scope of the present disclosure fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present disclosure is accordingly to be limited by nothing other than the appended claims, in which reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural, chemical, and functional equivalents to the elements of the above-described preferred embodiment(s) that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Moreover, it is not necessary for a device or method to address each and every problem sought to be solved by the present disclosure, for it to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. 

What is claimed is:
 1. An electrical interconnect adapted to provide an interface between contact pads on an IC device and a PCB, the electrical interconnect comprising: a multi-layered substrate with first and second major surfaces comprising a first dielectric layer with a plurality of first openings with first dielectric surfaces having first cross-sections, and a second dielectric layer with a plurality of second openings with second dielectric surfaces having second cross-sections, the multi-layered substrate comprising a plurality of center openings with center dielectric surfaces connecting the first and second openings, the center openings comprising at least one cross-section greater than the first and second cross-sections; a metalizing layer formed on at least one of the first dielectric surface, the second dielectric surface, or the center dielectric surface; a plurality of contact members located in the center openings, the contact members comprising first contact tips located in the first opening, second contact tips located in the second openings, and center portions located in the center openings, the center portions of the contact members comprise a shape adapted to bias the first and second contact tips toward the first and second major surfaces of the multi-layered substrate, respectively; and a dielectric material located on at least a portion of the metalizing layer to insulate the contact members from the metalizing layer.
 2. The electrical interconnect of claim 1 wherein the center openings comprise non-moldable feature.
 3. The electrical interconnect of claim 1 wherein at least the first contact tips extend above the first major surface of the multi-layered substrate.
 4. The electrical interconnect of claim 1 comprising metalized layers formed between layers in the substrate that electrically shield the contact members.
 5. The electrical interconnect of claim 1 wherein the dielectric material located on the metalizing layer is different from the dielectric material of the multi-layered substrate.
 6. The electrical interconnect of claim 1 wherein the metalizing layer is oriented generally parallel to the contact member.
 7. The electrical interconnect of claim 1 wherein the multilayered substrate comprises at least one additional circuitry plane selected from one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, or a flexible circuit.
 8. The electrical interconnect of claim 1 comprising at least one electrical device printed on the substrate and electrically coupled to at least a one of the contact members.
 9. An electrical interconnect assembly comprising: a housing that retains the electrical interconnect of claim 1; contact pads on an IC device biased into mechanical and electrical engagement with the first contact tips of the contact members; and a PCB biased into mechanical and electrically engagement with the second contact tips of the contact members.
 10. A method of making an electrical interconnect adapted to provide an interface between contact pads on an IC device and a PCB, the method comprising the steps of: forming a multi-layered substrate with first and second major surfaces comprising a first dielectric layer comprising a plurality of first openings with first dielectric surfaces having first cross-sections and a second dielectric layer comprising a plurality of second openings with second dielectric surfaces having second cross-sections; forming in the multi-layered substrate a plurality of center openings with center dielectric surfaces connecting the first and second openings, the center openings comprising at least one cross-section greater than the first and second cross-sections; metalizing at least one of the first dielectric surface, the second dielectric surface, or the center dielectric surface; locating a contact members in a plurality of the center openings so first contact tips of the contact members located in the first opening, second contact tips located in the second openings, and center portions located in the center openings bias the first and second contact tips toward the first and second major surfaces of the multi-layered substrate, respectively; and forming a dielectric material on at least a portion of the metalizing layer to insulate the contact members from the metalizing layer.
 11. The method of claim 10 comprising forming the center opening as non-moldable features.
 12. The method of claim 10 comprising locating the first contact tips of the first contact members above the first major surface of the multi-layered substrate.
 13. The method of claim 10 comprising forming a metal layers between layers in the substrate that electrically shield the contact members.
 14. The method of claim 10 wherein the dielectric material located on the metalizing layer is different from the material of the substrate.
 15. The method of claim 10 wherein the metalizing layer is oriented generally parallel to the contact member.
 16. The method of claim 10 comprising forming at least one additional circuitry plane between layers of the substrate, the additional circuitry plane selected from one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, or a flexible circuit.
 17. The method of claim 10 comprising printing at least one electrical device on the substrate and electrically coupling the electrical device to at least a one of the contact members.
 18. A method of making an electrical interconnect assembly comprising the steps of: locating the electrical interconnect of claim 10 in a housing; locating an integrated circuit device in the openings in the housing; electrically coupling the first contact tips of the contact members with the integrated circuit device; and electrically coupling the second contact tips of the contact members with the PCB.
 19. The method of claim 18 comprising the steps of biasing the integrated circuit device into mechanical and electrical engagement with the first contact tips of the contact members.
 20. The method of claim 18 comprising the steps of biasing the PCB into mechanical and electrical engagement with the second contact tips of the contact members. 